(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to prevent damage to copper lines during the process of polishing copper lines.
(2) Description of the Prior Art
The present invention relates to the creation of conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multilayer substrate on which semiconductor device(s) are mounted. The present invention specifically relates to the fabrication of conductive lines and vias by a process known as damascene. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. Copper damascene wiring is one of the most promising technologies to reduce RC delay as well as to implement the shrinkage of interconnect structures. For this, Chemical Mechanical Polishing (CMP) of inlaid copper is required to form the copper wiring. One of the major problems that is encountered when polishing inlaid copper patterns is the damage that is caused on the copper trench as a consequence of the polishing process. The invention addresses this concern and provides a novel method for damascene trench planarization by CMP processes.
Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
During the Chemical Mechanical Planarization (CMP) process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
It is well known in the art that, in the evolution of integrated circuit chips, the process of scaling down feature sizes results in making device performance more heavily dependent on the interconnections between devices.
In addition, the area required to route the interconnect lines becomes large relative to the area occupied by the devices. This normally leads to integrated circuit chips with multilevel interconnect lines. The chips are often mounted on multi-chip modules that contain buried wiring patterns to conduct electrical signals between the various chips. These modules usually contain multiple layers of interconnect metalization separated by alternating layers of an isolating dielectric.
Any conductor material to be used in a multilevel interconnect has to satisfy certain essential requirements such the underlying substrate material, stability (both electrical and mechanical) and ease of processing.
Copper is often preferred due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper unfortunately suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
Copper is typically very difficult to process using RIE technology as a consequence of which a method that uses CMP for copper wire formation offers significant advantages. To polish a buried copper wiring formation at a high polishing rate and without damaging the surface, the copper etch rate must be raised by increasing the amount of the component that is responsible for copper etching that is contained in the polishing slurry. If the component continues to be increased, the etching will occur isotropically whereby buried copper is etched away, causing dishing in the wiring. Thus, it is difficult to form a highly reliable LSI wiring made of copper.
FIG. 1 shows a Prior Art CMP apparatus. A polishing pad 20 is attached to a circular polishing table 22 that rotates in a direction indicated by arrow 24 at a rate in the order of 1 to 100 RPM. A wafer carrier 26 is used to hold wafer 18 facedown against the polishing pad 20. The wafer 18 is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer 18 can also be attached to the wafer carrier 26 by the application of a substrate attachment film (not shown) to the lower surface of the wafer carrier 26. The wafer carrier 26 also rotates as indicated by arrow 32, usually in the same direction as the polishing table 22, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table 22, the wafer 18 traverses a circular polishing path over the polishing pad 20. Slurry 23 is supplied to the surface of the wafer 18 that is being polished. A force 28 is also applied in the downward vertical direction against wafer 18 and presses the wafer 18 against the polishing pad 20 as it is being polished. The force 28 is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft 30 that is attached to the back of wafer carrier 26.
A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles.
Abrasive interaction between the wafer and the polishing pad is created by the motion of the wafer against the polishing pad. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals that comprise an insulating layer of the wafer. The size of the silicon dioxide particles controls the physical abrasion of surface of the wafer.
The polishing pad is typically fabricated from a polyurethane (such as non-fibrous polyurethane, cellular polyurethane or molded polyurethane) and/or a polyester-based material. Pads can for instance be specified as being made of a microporous blown polyurethane material having a planar surface and a Shore D hardness of greater than 35 (a hard pad). Semiconductor polishing pads are commercially available such as models IC1000 or Scuba IV of a woven polyurethane material.
FIGS. 2a through 2c show three cross-sections of copper depositions and patterns of damage that have been observed for each of these depositions.
FIG. 2a shows a planar view of a copper line 11 after line deposition and line planarization. An irregular plurality 10 of surface disruptions is apparent on the surface of the copper line. These disruptions 10 are caused by surface oxidation after line polishing or by line corrosion caused by interaction of the copper with slurry chemicals during the polishing of the copper line.
Experiments have indicated that the line damage 11 that is shown is dependent on and can therefore be influenced by the rate of slurry deposition on the surface that contains the copper lines during CMP. The rate of slurry deposition is defined as the volume, expressed in cubic-centimeter (cc), of slurry deposited during a given time, or as cc/minute.
Increased rate of slurry deposition results in a decrease of copper line surface damages. This experimental observation forms the basis for the invention in that the invention teaches a multi-step slurry deposition during the CMP of the copper lines whereby each step within the multi-step slurry deposition has a unique rate of slurry deposition.
FIG. 2b shows another form of copper line damage or irregularity that has been observed at the completion of the CMP of copper line 11. Copper line 11 is deposited on the surface of substrate 18. Area 12 is a hollowing out of the copper surface at the edge of the surface of the copper line 11 where this edge interfaces with the surrounding dielectric 16. This hollowing out has the profile of a semi-circle. Another irregularity is highlighted with 14, this irregularity also occurs on the surface of the copper line 11 where this line interfaces with the surrounding dielectric 16. This irregularity 14 has a sloping profile with the lowest point of the slope being at the sidewall of the opening that was created for the deposition of the copper line 11.
FIG. 2c shows yet another irregularity 17 that is typical and has been observed in the surface of the polished copper line 11. This irregularity 17 is typically referred to as a keyhole opening if the irregularity extends over a limited or concentrated section of the surface of the copper line 11. This surface irregularity can however also extend over a larger section of the surface of the copper line 11 and can, in this extension, follow the direction of a deposited copper line 11 over a considerable distance. In this case the irregularity is referred to as a surface seam in the copper line 11.
The process of the invention teaches a new polishing sequence and improved control over such polishing parameters as applied pressure during polishing, wafer carrier speed, slurry flow, belt speed and rinse time.
U.S. Pat. No. 5,893,756 (Berman et al.) teaches a cleaner after CMP.
U.S. Pat. No. 5,840,629 (Carpio) and U.S. Pat. No. 5,954,997 (Kaufman et al. show Cu CMP slurries and processes.
U.S. Pat. No. 5,722,877 (Meyer et al.) and U.S. Pat. No. 5,5,871,390 (Pant et al.) show CMP tools with adjustable belt parameters.
A principle objective of the invention is to reduce the impact of chemical surface reactions that are incurred between the steps of copper CMP and TaN-barrier CMP.
Another objective of the invention is to reduce the impact of chemical surface reactions that are incurred between the steps of TaN-barrier CMP and cleaning.
Another objective of the invention is to reduce surface abrasion and mechanical surface damage to copper lines during rinse cycles.
Yet another objective of the invention is to shorten the time delay that is required between the steps of copper CMP and TaN-barrier CMP.
Yet another objective of the invention is to shorten the time delay that is required between the steps of TaN-barrier CMP and cleaning.
Yet another objective of the invention is to improve the yield of the copper back-end-of-line (BEOL) process.
Yet another objective of the invention is to improve the reliability of the created copper lines.
In accordance with the objectives of the invention a new method is provided for the post-deposition treatment of copper lines. The invention has two embodiments. The process flow for the process of the first embodiment of the invention starts with the formation of a damascene or dual damascene pattern, a TaN barrier layer is deposited in the created opening overlying the bottom and the sidewalls of the opening. The seed layer is next deposited over the barrier layer, the opening of the damascene or dual damascene structure is filled with copper, the deposited copper is polished (Cu CMP) thereby completing the formation of the metal filled damascene or dual damascene structure. As a first step after Cu CMP, the surface of the wafer is rinsed using a first High Flow DI rinse that contains a TBA inhibitor. As a second step after Cu CMP, the step of TaN CMP is performed immediately following the first High Flow DI rinse whereby the TaN CMP is either time mode or until completion of the TaN CMP. As a third step after Cu CMP, a second High Flow DI rinse is applied using DI water that contains TBA to further clean the surface of the wafer. As a fourth step after Cu CMP, the required following rinse step is executed immediately after the second High Flow DI rinse has been completed. Under the second embodiment of the invention, the process of CMP has been divided in two distinct steps where the first step is aimed at corrosion elimination and the second step is aimed at elimination of mechanical damage to the polished copper. The processing conditions for the second processing step have been extended and optimized, thereby using a second belt of a CMP apparatus.